Partial Scan Design Based on Circuit State Information and Functional Analysis
IEEE Transactions on Computers
Eliminating the Timing Penalty of Scan
Journal of Electronic Testing: Theory and Applications
| Hi-index | 0.00 |
Test generation complexity varies exponentially as the depth of cycles in the S-graph of the circuit. We map the hard-to-reach states obtained from a sequential test generator onto the cycles in the S-graph of the circuit. We then proceed to rank the cycles in terms of the testability gain that would result if the cycle were broken. The primary objective is not to cut all the cycles but to cut those cycles which are preventing the test generator from reaching these hard-to-reach states. To this end, we introduce new measures that combine conventional testability measures such as controllability and observability with the information from hard-to-reach states. We show that this approach overcomes some of the limitations of conventional cycle-cutting. This selective cutting of cycles is shown to yield better results in terms of fault coverage than conventional cycle-cutting.