Distributed Test Pattern Generation for Stuck-At Faults in Sequential Circuits
Journal of Electronic Testing: Theory and Applications
ITEM: an iterative improvement test generation procedure for synchronous sequential circuits
GLSVLSI '01 Proceedings of the 11th Great Lakes symposium on VLSI
Exploiting symbolic techniques for partial scan flip flop selection
Proceedings of the conference on Design, automation and test in Europe
Test Synthesis with Alternative Graphs
IEEE Design & Test
Efficient Hierarchical Approach to Test Generation for Digital Systems
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
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Abstract: This paper presents a new approach to Automatic Test Pattern Generation for sequential circuits. Traditional topological algorithms nowadays are able to deal with very large circuits, but often fail when highly sequential subnetworks are found. On the other hand, symbolic techniques based on Binary Decision Diagrams proved themselves very efficient on small or medium circuits, no matter their sequential complexity. A state-of-the-art structural ATPG is extended by identifying some critical areas in the circuit and resorting to symbolic techniques when such areas need to be considered. Experimental results prove that the combined approach considerably enhances fault coverage while reducing CPU time when compared to a purely topological approach.