Software pipelining: an effective scheduling technique for VLIW machines
PLDI '88 Proceedings of the ACM SIGPLAN 1988 conference on Programming Language design and Implementation
Iterative modulo scheduling: an algorithm for software pipelining loops
MICRO 27 Proceedings of the 27th annual international symposium on Microarchitecture
A study of the cyclic scheduling problem on parallel processors
Discrete Applied Mathematics - Special issue: Combinatorial Optimization 1992 (CO92)
ACM Computing Surveys (CSUR)
Determining the minimum iteration period of an algorithm
Journal of VLSI Signal Processing Systems
A Framework for Resource-Constrained Rate-Optimal Software Pipelining
IEEE Transactions on Parallel and Distributed Systems
ILP-based cost-optimal DSP synthesis with module selection and data format conversion
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
List schedules for cyclic scheduling
Proceedings of the third international conference on Graphs and optimization
HAL: a multi-paradigm approach to automatic data path synthesis
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
On Graham's bound for cyclic scheduling
Parallel Computing - Special issue on new trends on scheduling in parallel and distributed systems
A comparative study of modulo scheduling techniques
ICS '02 Proceedings of the 16th international conference on Supercomputing
Scheduling Computer and Manufacturing Processes
Scheduling Computer and Manufacturing Processes
A Polynomial Time Method for Optimal Software Pipelining
CONPAR '92/ VAPP V Proceedings of the Second Joint International Conference on Vector and Parallel Processing: Parallel Processing
Logarithmic Number System and Floating-Point Arithmetics on FPGA
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
MICRO 14 Proceedings of the 14th annual workshop on Microprogramming
Scheduling of Iterative Algorithms on FPGA with Pipelined Arithmetic Unit
RTAS '04 Proceedings of the 10th IEEE Real-Time and Embedded Technology and Applications Symposium
Dynamic reconfiguration in FPGA-based SoC designs (abstract only)
Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays
Rotation scheduling: a loop pipelining algorithm
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Combined word-length optimization and high-level synthesis of digital signal processing systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Survey: Complexity of cyclic scheduling problems: A state-of-the-art survey
Computers and Industrial Engineering
A cyclic scheduling problem with an undetermined number of parallel identical processors
Computational Optimization and Applications
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This paper presents a scheduling technique used to optimize computation speed of loops running on architectures that may include pipelined dedicated processors. The problem under consideration is to find an optimal periodic schedule satisfying the timing constraints. Motivated by FPGA (Field-Programmable Gate Array) architecture we formulate a problem of cyclic scheduling on one dedicated processor where tasks are constrained by the precedence delays. Further we generalize this result to the set of dedicated processors. We also show how the set of constraints in both problems can be extended by start time related deadlines, multiprocessor tasks, changeover times and minimization of data transfers. We prove that this problem is NP-hard by reduction from Bratley's scheduling problem 1|r"j,d@?"j|C"m"a"x and we suggest a solution based on ILP (Integer Linear Programming) that allows one to minimize the completion time. Besides this, we suggest elimination of redundant constraints and binary variables in a integer linear programming model which leads to a speedup of the scheduling algorithm. Finally, experimental results are shown on an application of recursive least square filter and benchmarks.