Scheduling of Iterative Algorithms on FPGA with Pipelined Arithmetic Unit

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RTAS '04 Proceedings of the 10th IEEE Real-Time and Embedded Technology and Applications Symposium
Year:
2004

Citing 0
Cited 5

Scheduling of Iterative Algorithms with Matrix Operations for Efficient FPGA Design--Implementation of Finite Interval Constant Modulus Algorithm

Journal of VLSI Signal Processing Systems
Implementation of the least-squares lattice with order and forgetting factor estimation for FPGA

EURASIP Journal on Advances in Signal Processing
GSFAP adaptive filtering using log arithmetic for resource-constrained embedded systems

ACM Transactions on Embedded Computing Systems (TECS)
A graph-based analysis of the cyclic scheduling problem with time constraints: schedulability and periodicity of the earliest schedule

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Deadline constrained cyclic scheduling on pipelined dedicated processors considering multiprocessor tasks and changeover times

Mathematical and Computer Modelling: An International Journal

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Abstract

This paper presents a scheduling technique for a libraryof arithmetic logarithmic modules for FPGA illustrated ona RLS filter for active noise cancellation. The problem underassumption is to find an optimal periodic cyclic schedulesatisfying the timing constraints. The approach is basedon a transformation to monoprocessor cyclic schedulingwith precedence delays. We prove that this problem is NP-hard and we suggest a solution based on Integer Linear Programming that allows to minimize completion time. Finallyexperimental results of optimized RLS filter are shown.