HAL: a multi-paradigm approach to automatic data path synthesis
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
MAHA: a program for datapath synthesis
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
DAC '78 Proceedings of the 15th Design Automation Conference
Parallelism exposure and exploitation in programs
Parallelism exposure and exploitation in programs
Principles of Compiler Design (Addison-Wesley series in computer science and information processing)
Principles of Compiler Design (Addison-Wesley series in computer science and information processing)
Redundant operator creation: a scheduling optimization technique
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Recent developments in high-level synthesis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Analysis of different protocol description styles in VHDL for high-level synthesis
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Equivalent design representations and transformations for interactive scheduling
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
A Rule-Based Approach for Improving Allocation of Filter Structures in HLS
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
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A description is given of a process-graph analyzer, i.e. a program that optimizes an algorithmic hardware description while endeavoring to attain maximum speed with the minimum commitment to resources. The analyzer is part of the V-Synth system. The four major subsystems of the analyzer-the decomposer, the optimizer, the control-state generator, and the translator-are discussed. Because both its input and output are in VHDL, VHDL itself is discussed. Preliminary test results for the analyzer are presented.