HAL: a multi-paradigm approach to automatic data path synthesis
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
High-Level Power Analysis and Optimization
High-Level Power Analysis and Optimization
A Test Vector Ordering Technique for Switching Activity Reduction During Test Operation
GLS '99 Proceedings of the Ninth Great Lakes Symposium on VLSI
Efficient RTL Power Estimation for Large Designs
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Test Scheduling for Minimal Energy Consumption under Power Constraints
VTS '01 Proceedings of the 19th IEEE VLSI Test Symposium
System-Level Design Techniques for Energy-Efficient Embedded Systems
System-Level Design Techniques for Energy-Efficient Embedded Systems
VTS '05 Proceedings of the 23rd IEEE Symposium on VLSI Test
An Efficient Scan Chain Partitioning Scheme with Reduction of Test Data under Routing Constraint
DFT '06 Proceedings of the 21st IEEE International Symposium on on Defect and Fault-Tolerance in VLSI Systems
A Scan Chain Adjustment Technology for Test Power Reduction
ATS '06 Proceedings of the 15th Asian Test Symposium
On the Construction of Small Fully Testable Circuits with Low Depth
DSD '07 Proceedings of the 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools
A Knowledge-Based System for Designing Testable VLSI Chips
IEEE Design & Test
Probabilistic Testability Analysis and DFT Methods at RTL
DDECS '06 Proceedings of the 2006 IEEE Design and Diagnostics of Electronic Circuits and systems
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The paper presents testability analysis method that is based on partitioning circuit under analysis (CUA) into testable blocks (TBs). The concept of TBs is further utilized for power consumption reduction during the test application. Software tools which were developed during the research and integrated into the third party design flow are also described. The experimental results gained from the application of the methodology on selected benchmarks and practical designs are demonstrated. It was proven on the benchmarks, used for the verification of the methodology, that a fault coverage comparable to the partial scan method can be obtained. When combined with test vectors/scan cells reordering methodology significant power savings can be reached.