An Efficient Scan Chain Partitioning Scheme with Reduction of Test Data under Routing Constraint

Authors:
Geewhun Seok;Il-Soo Lee;Tony Ambler;B. F. Womack
Affiliations:
University of Texas at Austin, USA;University of Texas at Austin, USA;University of Texas at Austin, USA;University of Texas at Austin, USA
Venue:
DFT '06 Proceedings of the 21st IEEE International Symposium on on Defect and Fault-Tolerance in VLSI Systems
Year:
2006

Citing 0
Cited 2

Testability analysis based on the identification of testable blocks with predefined properties

Microprocessors & Microsystems
Incremental multiple-scan chain ordering for ECO flip-flop insertion

Proceedings of the International Conference on Computer-Aided Design

Quantified Score

Hi-index	0.00

Visualization

Abstract

A proposed scan chain partitioning scheme considers reduction of test set and test time, and the optimal routing inside each partitioned scan chain. First, two compatible scan cells are searched in input test set. One group of compatible scan cells is included in one partitioned scan chain, while the other group is in the other scan chain. In finding these compatible scan cells, the group-based approach is employed since it provides more optimal routing solution among the compatible scan cells in each of these two scan chains. After these two scan chains are filled with compatible scan cells, they will be able to share one of two compatible columns in input test set only during the shift-in process. Therefore, one of two compatible columns can be omitted from input test set and the scan operation. Results with ISCAS'89 benchmark circuits show that proposed method could reduce test data volume by 25-33% compared with a normal multiple scan design.