Arithmetic optimization using carry-save-adders
DAC '98 Proceedings of the 35th annual Design Automation Conference
ILP-based cost-optimal DSP synthesis with module selection and data format conversion
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Signal representation guided synthesis using carry-save adders for synchronous data-path circuits
Proceedings of the 38th annual Design Automation Conference
Layout-aware synthesis of arithmetic circuits
Proceedings of the 39th annual Design Automation Conference
Behavioural Transformation to Improve Circuit Performance in High-Level Synthesis
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Arrival time aware scheduling to minimize clock cycle length
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Performance-driven read-after-write dependencies softening in high-level synthesis
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Pre-synthesis optimization of multiplications to improve circuit performance
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Area optimization of multi-cycle operators in high-level synthesis
Proceedings of the conference on Design, automation and test in Europe
Performance-driven scheduling of behavioural specifications
Integration, the VLSI Journal
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Joint module selection and retiming is a powerful technique to optimize the implementation cost and the speed of a circuit specified using a synchronous data-flow graph (DFG). In implementing high-speed circuits, the use of carry-save signal representation is also a powerful technique to optimize the implementation cost and the speed of arithmetic circuits. This paper is the first to combine these two techniques to solve the joint module selection and retiming problem while allowing the use of carry-save representation. To solve this problem efficiently, we first propose a mixed-representation data-flow graph (MFG) that allows signals to be expressed in carry-save representation. We also propose techniques to accurately model the costs associated with different signal representations. In addition, we propose a solution-space pruning technique that significantly reduces the run-time of our algorithm. Our algorithm, by allowing carry-save representation, can produce a wider range of solutions. In our experiments, our fastest implementation is 28% faster and our smallest implementation is 47% smaller, in comparison to solutions obtained using the previously known joint module selection and retiming technique.