Register Allocation—A Hierarchical Reduction Approach

  • Authors:
  • Chaeryung Park;Taewhan Kim;C. L. Liu

  • Affiliations:
  • Synopsys Inc., 700 E. Middlefield Rd., Mountain View, CA 94043, USA;Department of Computer Science, Korea Advanced Institute of Science and Technology, Taejon, Korea;Tsing Hua University, Hsinchu, Taiwan R.O.C.

  • Venue:
  • Journal of VLSI Signal Processing Systems
  • Year:
  • 1998

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Abstract

A new approach to the problem of register allocation in high-level synthesis is presented. The algorithm employs a bottom-up transformational approach—sets of mutually exclusive variables in conditional branches are transformed into an “equivalent” set of nonmutuallyexclusive variables. The transformational approach is extended to the caseof data-flow graphs with loops. A new register allocation algorithm is thenused to produce an allocation for the nonmutually exclusive variables. Fromsuch an allocation, a corresponding allocation for the original set ofmutually exclusive variables is derived. Our approach is particularlyeffective when there is a large number of nested conditional branches andloops in a data-flow graph.