REAL: a program for REgister ALlocation
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
IEEE Transactions on Computers
Understanding retiming through maximum average-delay cycles
Proceedings of the 3rd ACM symposium on Parallel algorithms and architectures
MediaBench: a tool for evaluating and synthesizing multimedia and communicatons systems
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
Timing analysis and optimization of sequential circuits
Timing analysis and optimization of sequential circuits
Register binding and port assignment for multiplexer optimization
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Register binding for clock period minimization
Proceedings of the 43rd annual Design Automation Conference
Early planning for clock skew scheduling during register binding
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Retiming and clock scheduling for digital circuit optimization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
FPGA latency optimization using system-level transformations and DFG restructuring
Proceedings of the Conference on Design, Automation and Test in Europe
| Hi-index | 0.03 |
This paper points out that register binding in the high-level synthesis stage has a significant impact on the clocking constraints between registers. As a result, different register binding solutions often lead to different smallest feasible clock periods. Based on that observation, we formally draw up the problem of register binding for clock-period minimization. Compared with the left edge algorithm, experimental data show that, in most benchmark circuits, our approach can greatly reduce the clock period without any overhead on the number of registers.