A low power based system partitioning and binding technique for multi-chip module architectures

Authors:
R. V. Cherabuddi;M. A. Bayoumi;H. Krishnamurthy
Affiliations:
-;-;-
Venue:
GLS '97 Proceedings of the 7th Great Lakes Symposium on VLSI
Year:
1997

Citing 0
Cited 2

Combined functional partitioning and communication speed selection for networked voltage-scalable processors

Proceedings of the 15th international symposium on System Synthesis
Energy Optimization of Distributed Embedded Processors by Combined Data Compression and Functional Partitioning

Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design

Quantified Score

Hi-index	0.00

Visualization

Abstract

In this paper, we present a low power targeted high-level synthesis framework for the synthesis of Multi-Chip Modules (MCM). This new framework is based on minimizing the switching activity on the functional units as well as the inter-chip buses. The main focus of the developed method is minimizing the power during partitioning and binding phases of high-level synthesis. A Stochastic Evolution based technique has been used for system partitioning. Experimental results were highly encouraging with power reduction of up to 60% on certain benchmark designs.