The turn model for adaptive routing
ISCA '92 Proceedings of the 19th annual international symposium on Computer architecture
The Odd-Even Turn Model for Adaptive Routing
IEEE Transactions on Parallel and Distributed Systems
Interconnection Networks: An Engineering Approach
Interconnection Networks: An Engineering Approach
Principles and Practices of Interconnection Networks
Principles and Practices of Interconnection Networks
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Deadlock-free routing and component placement for irregular mesh-based networks-on-chip
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Routing table minimization for irregular mesh NoCs
Proceedings of the conference on Design, automation and test in Europe
DSD '07 Proceedings of the 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools
IEEE Transactions on Computers
Introduction to Algorithms, Third Edition
Introduction to Algorithms, Third Edition
Design of multi-channel wireless NoC to improve on-chip communication capacity
NOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip
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To bridge the widening gap between computation requirements of terascale application and communication efficiency faced by gigascale multi-processor system-on-chip devices, a new on-chip communication system, dubbed Wireless Network-on-Chip (WNoC), has been proposed. This work centers on the design of a high-efficient, low-cost, deadlock-free routing scheme for domain-specific irregular mesh WNoCs. A distributed minimal table based routing scheme is designed to facilitate segmented XY-routing. Deadlock-free data transmission is achieved by implementing a new turn classes based buffer ordering scheme. The simulation study demonstrates high routing efficiency, low cost and scalability of the routing scheme and the promising network performance of WNoC.