The SPLASH-2 programs: characterization and methodological considerations
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
IEEE Transactions on Computers
Interconnect opportunities for gigascale integration
IBM Journal of Research and Development
A Low-Cost Deadlock-Free Design of Minimal-Table Rerouted XY-Routing for Irregular Wireless NoCs
NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
Position-based routing in ad hoc networks
IEEE Communications Magazine
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Many-core chip design has become a popular means to sustain the exponential growth of chip-level computing performance. The main advantage lies in the exploitation of parallelism, distributively and massively. Consequently, the on-chip communication fabric becomes the performance determinant. In the meantime, the introduction of Ultra-Wideband (UWB) interconnect brings in the new opportunity for giga-bps communication bandwidth, milliwatts communication power, and low cost implementation for millimeter range on-chip communication for future chip generations. In this paper, we study multi-channel wireless Network-on-Chip (McWiNoC) with ultra-short RF/wireless links for multi-hop communication. We first present the benefit of high bandwidth, low latency and flexible topology configurations provided by this new on-chip interconnection network. We then propose a distributed and deadlock-free location based routing scheme. We further design an efficient channel arbitration scheme to grant multi-channel access. With a few representative synthetic traffic patterns and SPLASH-II benchmarks, we demonstrate that McWiNoC can achieve 23.3% average performance improvement and 65.3% average end-to-end latency reduction over a baseline NoC of 8 x 8 metal wired mesh.