Leveraging partially faulty links usage for enhancing yield and performance in networks-on-chip
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fault tolerant network on chip switching with graceful performance degradation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special issue on the 2009 ACM/IEEE international symposium on networks-on-chip
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In this paper we propose a series of efficient routing strategies to effectively utilize NoC systems with partially faulty links. These strategies try to use partially faulty links when the load is high and distribute traffic uniformly on links. Evaluation of our strategies for 8x8 mesh with 7% partially faulty links shows that, using our best strategy, it is possible to achieve an average reduction of up to 50% on packet delay when the load is high. We have also worked out complete designs of routers which can tolerate partial link faults and implement our routing strategies. Approximately 25% extra area and 5% extra power consumption is required for the design of the upgraded router incorporating link fault tolerance and the best routing strategy. However, the overall performance improvement counter balances such overhead resulting in an overall saving in energy consumption of up to 20%. The proposed strategies offer a way to increase the effective yield of large and complex NoC systems.