A new mechanism to deal with process variability in NoC links

Authors:
Carles Hernandez;Federico Silla;Vicente Santonja;Jose Duato
Affiliations:
Parallel Architecture Group, Universidad Politécnica de Valencia, Camino de Vera s/n, 46022, Spain;Parallel Architecture Group, Universidad Politécnica de Valencia, Camino de Vera s/n, 46022, Spain;Parallel Architecture Group, Universidad Politécnica de Valencia, Camino de Vera s/n, 46022, Spain;Parallel Architecture Group, Universidad Politécnica de Valencia, Camino de Vera s/n, 46022, Spain
Venue:
IPDPS '09 Proceedings of the 2009 IEEE International Symposium on Parallel&Distributed Processing
Year:
2009

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Abstract

Associated with the ever growing integration scale of VLSI technologies is the increase in process variability, which makes silicon devices to become less predictable. In the context of network-on-chip (NoC), this variability affects the maximum frequency that could be sustained by each wire of the link that interconnects two cores in a CMP system.