A novel graceful degradable routing algorithm for 3D on-chip networks
Proceedings of the 2012 Interconnection Network Architecture: On-Chip, Multi-Chip Workshop
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As the complexity of the integrated circuits increases, they become more susceptible to manufacturing faults, decreasing the total process yield. Thus, it would be desirable to develop techniques for reusing faulty dies, even with a degraded performance. In this paper, a new method for high level synthesis of degradable ASICs is presented. Our technique introduces the concept of Virtual Binding. In this approach, the operations are bound to virtual components that are linked with actual non-faulty components using a set of configuration multiplexers and flip-flops embedded in the data-path. Using virtual components simplifies the synthesis algorithm and decreases the size of generated control unit. Virtual-to-physical mapping of the components will be established by programming the configuration flip-flops after diagnosing the faulty components. The experimental results show that the area and delay overhead of the resulting circuits have acceptable values compared to the original, non-degradable circuits.