Performance evaluation for application-specific architectures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Efficient software performance estimation methods for hardware/software codesign
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Computer architecture (2nd ed.): a quantitative approach
Computer architecture (2nd ed.): a quantitative approach
Surviving the SOC revolution: a guide to platform-based design
Surviving the SOC revolution: a guide to platform-based design
System synthesis for multiprocessor embedded applications
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Retargetable estimation scheme for DSP architecture selection
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Performance Modeling for Computer Architects
Performance Modeling for Computer Architects
Codesign of Embedded Systems: Status and Trends
IEEE Design & Test
Deep-Submicron Microprocessor Design Issues
IEEE Micro
Compilation-based software performance estimation for system level design
HLDVT '00 Proceedings of the IEEE International High-Level Validation and Test Workshop (HLDVT'00)
Mappability Estimation of Architecture and Algorithm
Proceedings of the conference on Design, automation and test in Europe
System-level design: orthogonalization of concerns and platform-based design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Extending Platform-Based Design to Network on Chip Systems
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
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Mappability metric and a novel method for evaluating the goodness of processor core and algorithm combinations are introduced. The new mappability concept is an addition to performance and cost metrics used in existing codesign and system synthesis approaches. The mappability estimation is based on the analysis of the correlation or similarity of algorithm and core architecture characteristics. It allows fast design space exploration of core architectures and mappings with little modeling effort. The method is demonstrated by analyzing suitable processor core architectures for baseband algorithms of the WLAN modem. 140400 architecture-algorithm pairs were analyzed in total and the estimated results were similar to the results of more detailed evaluations. The method is not, however, limited to the WLAN modem, but is applicable for digital signal processing in general.