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Evolution of Parallel Cellular Machines: The Cellular Programming Approach
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ICES '98 Proceedings of the Second International Conference on Evolvable Systems: From Biology to Hardware
ICES '98 Proceedings of the Second International Conference on Evolvable Systems: From Biology to Hardware
Embryonics: A Macroscopic View of the Cellular Architecture
ICES '98 Proceedings of the Second International Conference on Evolvable Systems: From Biology to Hardware
Structure-Adaptable Neurocontrollers: A Hardware-Friendly Approach
IWANN '97 Proceedings of the International Work-Conference on Artificial and Natural Neural Networks: Biological and Artificial Computation: From Neuroscience to Technology
FPL '97 Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications
XC6200 FastmapTM Processor Interface
FPL '95 Proceedings of the 5th International Workshop on Field-Programmable Logic and Applications
Implementing Reconfigurable Datapaths in FPGAs for Adaptive Filter Design
FPL '96 Proceedings of the 6th International Workshop on Field-Programmable Logic, Smart Applications, New Paradigms and Compilers
Reconfigurable Architectures for General-Purpose Computing
Reconfigurable Architectures for General-Purpose Computing
Constructive Incremental Learning from Only Local Information
Neural Computation
A phylogenetic, ontogenetic, and epigenetic view of bio-inspired hardware systems
IEEE Transactions on Evolutionary Computation
Evolving hardware by dynamically reconfiguring xilinx FPGAs
ICES'05 Proceedings of the 6th international conference on Evolvable Systems: from Biology to Hardware
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In this paper we shall address the possibility of incorporating a new degree of freedom in the design of electronic systems. It consists of providing the ability to evolve its internal meso-structure while in operation. This new design strategy is allowed by the features included in a new family of FPGA devices, which is called FIPSOC (Field Programmable System On a Chip). Besides a programmable digital section composed of an array of LUT-like configurable cells, the device includes a configurable analog part and a general purpose microcontroller. Furthermore, the configuration scheme used for the programmable digital section allows for an efficient and fast realisation of dynamic reconfiguration principles. As we shall show in this paper, these properties offer two new on-line hardware evolution strategies, giving rise to what we have called virtual meso-structures.