An embedded DRAM architecture for large-scale spatial-lattice computations

Authors:
Norman Margolus
Affiliations:
Boston University Center for Computational Science, 3 Cummington Street, Boston and MIT AI Laboratory, 545 Technology Square, Cambridge, MA
Venue:
Proceedings of the 27th annual international symposium on Computer architecture
Year:
2000

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Abstract

Spatial-lattice computations with finite-range interactions are an important class of easily parallelized computations. This class includes many simple and direct algorithms for physical simulation, virtual-reality simulation, agent-based modeling, logic simulation, 2D and 3D image processing and rendering, and other volumetric data processing tasks. The range of applicability of such algorithms is completely dependant upon the lattice-sizes and processing speeds that are computationally feasible. Using embedded DRAM and a new technique for organizing SIMD memory and communications we can efficiently utilize 1 Tbit/sec of sustained memory bandwidth in each chip in an indefinitely scalable array of chips. This allows a 10,000-fold speedup per memory chip for these algorithms compared to the CAM-8 lattice gas computer, and is about one million times faster per memory chip for these calculations than a CM-2.