Field-programmable gate arrays
Field-programmable gate arrays
An architecture for a DSP field-programmable gate array
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
A reconfigurable arithmetic array for multimedia applications
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
The design of a SRAM-based field-programmable gate array—part II: circuit design and layout
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Architecture and CAD for Deep-Submicron FPGAs
Architecture and CAD for Deep-Submicron FPGAs
VPR: A new packing, placement and routing tool for FPGA research
FPL '97 Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications
Reconfigurable Processing: The Solution to Low-Power Programmable DSP
ICASSP '97 Proceedings of the 1997 IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP '97) -Volume 1 - Volume 1
Reconfigurable Architectures for General-Purpose Computing
Reconfigurable Architectures for General-Purpose Computing
An FPGA architecture with enhanced datapath functionality
FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays
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Reconfigurable Computing (RC) has already been proved as a cost-efficient solution for rapid prototypingan d some low-volume applications. Today, RC also gains importance in the context of embedded systems. However, mature and fully developed reconfigurable logic solutions for such systems are still missing. The primary reasons for this are the intrinsic cost of reconfigurable logic, and dedicated process technologies that reconfigurable designs are usually based on. In this paper, we present a novel reconfigurable logic core which addresses these issues. A logic cell architecture of the core has been tuned to a single application domain only (application-specific kernels in DSP applications). This allowed a reduction of the required amount of routingre sources by 28% compared with a commercial FPGA architecture. The core has been implemented in a standard CMOS 0.13碌m process technology.