A dynamically reconfigurable hardware-based cipher chip

Authors:
Yukio Mitsuyama;Zaldy Andales;Takao Onoye;Isao Shirakawa
Affiliations:
Dept. Information Systems Eng., Osaka University, 2-1 Yamada-Oka, Suita, Osaka, 565-0871 Japan;Dept. Information Systems Eng., Osaka University, 2-1 Yamada-Oka, Suita, Osaka, 565-0871 Japan;Dept. Communications & Computer Eng., Kyoto University, Yoshida-Honmachi, Sakyo-ku, Kyoto, 606-8501 Japan;Dept. Information Systems Eng., Osaka University, 2-1 Yamada-Oka, Suita, Osaka, 565-0871 Japan
Venue:
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Year:
2001

Citing 3
Cited 0

PipeRench: A Reconfigurable Architecture and Compiler

Computer
Garp: a MIPS processor with a reconfigurable coprocessor

FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
Reconfigurable Architectures for General-Purpose Computing

Reconfigurable Architectures for General-Purpose Computing

Quantified Score

Hi-index	0.00

Visualization

Abstract

A cipher core has been implemented, which is dedicated to a 64-bit block, 128-bit key, dynamically reconfigurable hardware-based cipher, called "Chameleon", in which two 32-cell, 8-context dynamically reconfigurable hardware units are employed to generate new subkeys for each of the 16 iterations in the encryption/decryption process. The proposed architecture has been implemented by 0.6 um CMOS3LM technology, using 65.6K transistors and attaining a maximum throughput of 317.5 Mbps. The new approach demonstrates distinctive features of enhanced complexity and flexibility dedicatedly for embedded encryption/decryption applications in the mobile computing.