Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays
Hybrid product term and LUT based architectures using embedded memory blocks
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
A decade of reconfigurable computing: a visionary retrospective
Proceedings of the conference on Design, automation and test in Europe
Routing Architectures for Hierarchical Field Programmable Gate Arrays
ICCS '94 Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors
The Design of a New FPGA Architecture
FPL '95 Proceedings of the 5th International Workshop on Field-Programmable Logic and Applications
Reconfigurable Architectures for General-Purpose Computing
Reconfigurable Architectures for General-Purpose Computing
Scalable defect mapping and configuration of memory-based nanofabrics
HLDVT '05 Proceedings of the High-Level Design Validation and Test Workshop, 2005. on Tenth IEEE International
FPGA Design Automation: A Survey
Foundations and Trends in Electronic Design Automation
MBARC: a scalable memory based reconfigurable computing framework for nanoscale devices
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
A circuit-software co-design approach for improving EDP in reconfigurable frameworks
Proceedings of the 2009 International Conference on Computer-Aided Design
A variation-aware preferential design approach for memory based reconfigurable computing
Proceedings of the 2009 International Conference on Computer-Aided Design
Computing with nanoscale memory: Model and architecture
NANOARCH '09 Proceedings of the 2009 IEEE/ACM International Symposium on Nanoscale Architectures
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Conventional FPGA architectures leverage on the spatial computing model where the design to be realized is represented in the form of multi-input single-output lookup tables (LUTs). However, such a model incorporates a reconfigurable interconnect network which leads to significant design overhead and poor scalability with process technology. In this paper, we propose a multi-cycle Memory Based Computational methodology that utilizes Content Addressable Memory (CAM) as the underlying reconfigurable fabric. The use of CAM in the proposed framework leads to significant reduction in memory requirement compared to LUT-based approach. Simulation results for standard benchmark circuits indicate that the proposed CAM based implementation improves the memory requirement significantly compared to its LUT counterpart, at the cost of little or no degradation in performance.