Detection of SRAM cell stability by lowering array supply voltage
ATS '00 Proceedings of the 9th Asian Test Symposium
Process variation tolerant low power DCT architecture
Proceedings of the conference on Design, automation and test in Europe
MBARC: a scalable memory based reconfigurable computing framework for nanoscale devices
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Proceedings of the 45th annual Design Automation Conference
Design and Analysis of a Self-Repairing SRAM with On-Chip Monitor and Compensation Circuitry
VTS '08 Proceedings of the 26th IEEE VLSI Test Symposium
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Hi-index | 0.00 |
Static Random Access Memory (SRAM) arrays designed in sub-90nm technologies are highly vulnerable to process variation induced read/write/access failures. In memory based reconfigurable computing frameworks, which use large high density memory array, such failures lead to incorrect execution of mapped applications. It causes loss in Quality of Service (QoS) for Digital Signal Processing (DSP) applications. We propose a "Preferential Design" approach at both application mapping and circuit level, which can significantly improve QoS and yield under large parameter variations. Such a architecture/circuit co-design approach can also tolerate increased failure rate at low operating voltage, thus facilitating low-power operation. Simulation results for a common DSP application show 45% improvement in power at iso--QoS and 47% in yield for a target Peak Signal to Noise Ratio (PSNR) at 45nm technology.