Network-based heuristics for constraint-satisfaction problems
Artificial Intelligence
An affine partitioning algorithm to maximize parallelism and minimize communication
ICS '99 Proceedings of the 13th international conference on Supercomputing
A Glimpse of Constraint Satisfaction
Artificial Intelligence Review
Parallelizing DSP nested loops on reconfigurable architectures using data context switching
Proceedings of the 38th annual Design Automation Conference
An energy saving strategy based on adaptive loop parallelization
Proceedings of the 39th annual Design Automation Conference
On the Parallel Execution Time of Tiled Loops
IEEE Transactions on Parallel and Distributed Systems
A GSA-based compiler infrastructure to extract parallelism from complex loops
ICS '03 Proceedings of the 17th annual international conference on Supercomputing
Automatic Loop Parallelization: An Abstract Interpretation Approach
PARELEC '02 Proceedings of the International Conference on Parallel Computing in Electrical Engineering
An Approach to Parallelizing Non-Uniform Loops with the Omega Calculator
PARELEC '02 Proceedings of the International Conference on Parallel Computing in Electrical Engineering
Constraint Processing
Compiler Techniques for the Distribution of Data and Computation
IEEE Transactions on Parallel and Distributed Systems
Automatic parallel code generation for tiled nested loops
Proceedings of the 2004 ACM symposium on Applied computing
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
A Constraint Network Based Approach to Memory Layout Optimization
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Exploitation of parallelism to nested loops with dependence cycles
Journal of Systems Architecture: the EUROMICRO Journal
Integrating loop and data optimizations for locality within a constraint network based framework
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
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Increasing employment of chip multiprocessors in embedded computing platforms requires a fresh look at conventional code parallelization schemes. In particular, any compiler-based parallelization scheme for chip multiprocessors should account for the fact that interprocessor communication is cheaper than off-chip memory accesses in these architectures. Based on this observation, this paper proposes a constraint network based approach to code parallelization for chip multiprocessors. Constraint networks have proven to be a useful mechanism for modeling and solving computationally intensive tasks in artificial intelligence. They operate by expressing a problem as a set of variables, variable domains and constraints and define a search procedure that tries to satisfy the constraints (an acceptable subset of them) by assigning values to variables from their specified domains. This paper demonstrates that it is possible to use a constraint network based formulation for the problem of code parallelization for chip multiprocessors. Our experimental evaluation shows that not only a constraint network based approach is feasible for our problem but also highly desirable since it outperforms all other parallelization schemes tested in our experiments.