The implementation of the Cilk-5 multithreaded language
PLDI '98 Proceedings of the ACM SIGPLAN 1998 conference on Programming language design and implementation
SODA: A Low-power Architecture For Software Radio
Proceedings of the 33rd annual international symposium on Computer Architecture
Sequoia: programming the memory hierarchy
Proceedings of the 2006 ACM/IEEE conference on Supercomputing
CellSs: a programming model for the cell BE architecture
Proceedings of the 2006 ACM/IEEE conference on Supercomputing
Vector processing as an enabler for software-defined radio in handheld devices
EURASIP Journal on Applied Signal Processing
The sandbridge SB3011 platform
EURASIP Journal on Embedded Systems
A coarse-grained array based baseband processor for 100Mbps+ software defined radio
Proceedings of the conference on Design, automation and test in Europe
Low Power Methodology Manual: For System-on-Chip Design
Low Power Methodology Manual: For System-on-Chip Design
Bridging dream and reality: programmable baseband processors for software-defined radio
IEEE Communications Magazine
Self-aware heterogeneous MPSoC with dynamic task scheduling for battery lifetime extension
CHANGE '11 Proceedings of the 2011 1st International Workshop on Computing in Heterogeneous, Autonomous 'N' Goal-Oriented Environments
Instruction Set Architecture Extensions for a Dynamic Task Scheduling Unit
ISVLSI '12 Proceedings of the 2012 IEEE Computer Society Annual Symposium on VLSI
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Heterogeneity and parallelism in MPSoCs for 4G (and beyond) communications signal processing are inevitable in order to meet stringent power constraints and performance requirements. The question arises on how to cope with the problem of system programmability and runtime management incurred by the statically or even dynamically varying number and type of processing elements. This work addresses this challenge by proposing the concept of a heterogeneous many-core platform called Tomahawk. Apart from the definition of the system architecture, in this approach a unified framework including a model of computation, a programming interface and a dedicated runtime management unit called CoreManager is proposed. The increase of system complexity in terms of application parallelism and number of resources may lead to a dramatic increase of the management costs, hence causing performance degradation. For this reason, the efficient implementation of the CoreManager becomes a major issue in system design. This work compares the performance and capabilities of various CoreManager HW/SW solutions, based on ASIC, RISC and ASIP paradigms. The results demonstrate that the proposed ASIP-based solution approaches the performance of the ASIC realization, while preserving the full flexibility of the software (RISC-based) implementation.