Space-Time Wireless Systems: From Array Processing to MIMO Communications
Space-Time Wireless Systems: From Array Processing to MIMO Communications
Low power soft-output signal detector design for wireless MIMO communication systems
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Relaxed K-best MIMO signal detector design and VLSI implementation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the Conference on Design, Automation and Test in Europe
Algorithm and implementation of the K-best sphere decoding for MIMO detection
IEEE Journal on Selected Areas in Communications
Soft-output sphere decoding: algorithms and VLSI implementation
IEEE Journal on Selected Areas in Communications
A low cost multi-standard near-optimal soft-output sphere decoder: algorithm and architecture
Proceedings of the Conference on Design, Automation and Test in Europe
Exploration of Soft-Output MIMO Detector Implementations on Massive Parallel Processors
Journal of Signal Processing Systems
High-throughput soft-output MIMO detector based on path-preserving trellis-search algorithm
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Energy-efficient scalable soft-output signal detectors are of significant interest in emerging Multiple-Input Multiple-Output (MIMO) wireless communication systems. However, traditional high-performance MIMO detectors consume a rather high amount of power, are typically constraint to one modulation scheme and are not scalable with the number of antennas. Hence, they are not well-suited for future energy-efficient Software Defined Radio (SDR) platforms. This paper presents two energyefficient scalable MIMO detector architectures: one optimized for high throughput, one for low area. Both architectures support 16-QAM as well as 64-QAM while offering soft-output and near-ML performance. The 2×2 high-throughput architecture was implemented in CMOS 65nm technology and subsequently scaled to 4×4 and 8×8. The 4×4 instance provides up to 300Mbps throughput while consuming only 0.3mm2 area and 28mW power. The 8×8 instance offers a throughput 10× better than the state-of-the-art while consuming 2/3 less power. Thus, the proposed near-ML Selective Spanning with Fast Enumeration (SSFE) based detector architectures are not only multistandard capable and scalable, they are also highly efficient.