Lattice basis reduction: improved practical algorithms and solving subset sum problems
Mathematical Programming: Series A and B
On Limits of Wireless Communications in a Fading Environment when UsingMultiple Antennas
Wireless Personal Communications: An International Journal
Vector processing as an enabler for software-defined radio in handheld devices
EURASIP Journal on Applied Signal Processing
Relaxed K-best MIMO signal detector design and VLSI implementation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Novel energy-efficient scalable soft-output SSFE MIMO detector architectures
SAMOS'09 Proceedings of the 9th international conference on Systems, architectures, modeling and simulation
The Chase Family of Detection Algorithms for Multiple-Input Multiple-Output Channels
IEEE Transactions on Signal Processing
Algorithm and implementation of the K-best sphere decoding for MIMO detection
IEEE Journal on Selected Areas in Communications
Soft-output sphere decoding: algorithms and VLSI implementation
IEEE Journal on Selected Areas in Communications
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We present an algorithm and architecture of a soft-output sphere decoder with an optimized hardware implementation for 2x2 MIMO-OFDM reception. We introduce a novel table look-up approach for symbol enumeration that simplifies the implementation of soft-output decoders. The HW implementation is targeted towards WLAN (IEEE 802.11n) with stringent latency and throughput requirements. The current implementation supports all modulation schemes (BPSK, QPSK, 16-QAM, 64-QAM) and shows near-optimal real-time performance. To achieve this, the sphere decoder computes in the worst-case Euclidean distances of 4.1 Giga QAM symbols per second. This challenging requirement is met by a scalable, multi-standard HW architecture which can be tuned to other applications such as LTE, WiMax with no re-design effort. The current instance for WLAN occupies an area of only 0.17 mm2 in 45 nm CMOS technology while providing a guaranteed throughput of 374 Msoftbits/s at 312 MHz clock rate (i.e. outputting 2x6 softbits worst-case every 10 clock cycles).