An energy-efficient reconfigurable baseband processor for wireless communications

Authors:
Ada S. Y. Poon
Affiliations:
Department of Electrical and Computer Engineering, University of Illinois, Urbana-Champaign, IL
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2007

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Abstract

Most existing techniques for reconfigurable processors focus on the computation model. This paper focuses on increasing the granularity of configurable units without compromising flexibility. This is carried out by matching the granularity to the degree-of-freedom processing in most wireless systems. A design flow that accelerates the exploration of tradeoffs among various architectures for the configurable unit is discussed. A prototype processor is implemented using the Intel 0.13-µm CMOS standard cell library. The estimated energy efficiency is in the same order as dedicated hardware implementations.