ACM Computing Surveys (CSUR)
Modulo scheduling with integrated register spilling for clustered VLIW architectures
Proceedings of the 34th annual ACM/IEEE international symposium on Microarchitecture
Swing Modulo Scheduling: A Lifetime-Sensitive Approach
PACT '96 Proceedings of the 1996 Conference on Parallel Architectures and Compilation Techniques
Proceedings of the 1st international conference on Embedded networked sensor systems
Register Constrained Modulo Scheduling
IEEE Transactions on Parallel and Distributed Systems
Architecture Exploration for a Reconfigurable Architecture Template
IEEE Design & Test
Modulo graph embedding: mapping applications onto coarse-grained reconfigurable architectures
CASES '06 Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems
The Journal of Supercomputing
Recurrence cycle aware modulo scheduling for coarse-grained reconfigurable architectures
Proceedings of the 2009 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
Nonlinear inertia weight variation for dynamic adaptation in particle swarm optimization
Computers and Operations Research
Hi-index | 0.00 |
Coarse-Grained Reconfigurable Architectures CGRAs have gained currency in recent years due to their abundant parallelism and flexibility. To utilize the parallelism found in CGRAs, this paper proposes a fast and efficient Modulo-Constrained Hybrid Particle Swarm Optimization MCHPSO scheduling algorithm to exploit loop-level parallelism in applications. This paper shows that Particle Swarm Optimization PSO is capable of software pipelining loops by overlapping placement, scheduling and routing of successive loop iterations and executing them in parallel. The proposed algorithm has been experimentally validated on various DSP benchmarks under two different architecture configurations. These experiments indicate that the proposed MCHPSO algorithm can find schedules with small initiation intervals within a reasonable amount of time. The MCHPSO scheduling algorithm was analyzed with different topologies and Functional Unit FU configurations. The authors have tested the parallelizability of the algorithm and found that it exhibits a nearly linear speedup on a multi-core CPU.