Exploiting dynamic reconfiguration techniques: the 2D-VLIW approach

Authors:
Ricardo Santos;Rodolfo Azevedo;Guido Araujo
Affiliations:
State University of Campinas, Institute of Computing, Campinas, SP, Brazil and Dom Bosco Catholic University, Dept. of Computer Engineering, Campo Grande, MS, Brazil;State University of Campinas, Institute of Computing, Campinas, SP, Brazil;State University of Campinas, Institute of Computing, Campinas, SP, Brazil
Venue:
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
Year:
2006

Citing 6
Cited 2

Multiple-banked register file architectures

Proceedings of the 27th annual international symposium on Computer architecture
PipeRench: A Reconfigurable Architecture and Compiler

Computer
Garp: a MIPS processor with a reconfigurable coprocessor

FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
Very Long Instruction Word architectures and the ELI-512

ISCA '83 Proceedings of the 10th annual international symposium on Computer architecture
Architecture Exploration for a Reconfigurable Architecture Template

IEEE Design & Test
Trimaran: an infrastructure for research in instruction-level parallelism

LCPC'04 Proceedings of the 17th international conference on Languages and Compilers for High Performance Computing

Function-level multitasking interface design in an embedded operating system with reconfigurable hardware

EUC'07 Proceedings of the 2007 international conference on Embedded and ubiquitous computing
A pattern based instruction encoding technique for high performance architectures

International Journal of High Performance Systems Architecture

Quantified Score

Hi-index	0.00

Visualization

Abstract

Fast reconfiguration is a mandatory feature for reconfigurable computing architectures. Research in this area has been increasingly focusing on new reconfiguration techniques that can sustain the architecture performance and to allow the simultaneous execution, at the same stage, of configuration and computation tasks. In this context, this paper presents a new dynamic reconfiguration technique, based on a configuration cache, that tackles this challenge by configuring and executing operations on functional units during the execution stage. This approach is implemented in a pipelined reconfigurable multiple-issue architecture called 2D-VLIW. Our dynamic reconfiguration technique takes advantage of the 2D-VLIW pipelined execution by starting reconfiguration concurrently to activities like reading operand registers and executing operations.