Microc/OS-II
Optimization of Reconfiguration Overhead by Algorithmic Transformations and Hardware Matching
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 3 - Volume 04
An overview of reconfigurable hardware in embedded systems
EURASIP Journal on Embedded Systems
ReConfigME: a detailed implementation of an operating system for reconfigurable computing
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
Exploiting dynamic reconfiguration techniques: the 2D-VLIW approach
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
Reduce SW/HW migration efforts by a RTOS in Multi-FPGA systems
CSCWD'05 Proceedings of the 9th international conference on Computer Supported Cooperative Work in Design II
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Reconfigurable architecture provides a high performance computing paradigm. We can implement the compute-intensive functions into reconfigurable devices to optimize the application performance. In current reconfigurable hardware designs, the function-level reconfigurable hardware has high reusability and low maintenance cost. However, the sharing mechanism and the function invocation interface are still unknown. In this paper, we propose a function-level multitasking interface design to support reconfigurable component sharing in a multitasking embedded operating system. The reconfigurable hardware functions are managed and scheduled by the operating system. Applications can use any needed hardware function via invocation APIs. To study the performance impacts, we implemented a prototype on Altera SOPC development board. We modified µC/OS-II RTOS and evaluated the prototype with prime number search programs and loop programs. The experimental results show the management overhead is acceptable.