Proceedings of the conference on Design, automation and test in Europe
Automating Production of Run-Time Reconfigurable Designs
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
Algorithm Partitioning including Optimized Data-Reuse for Processor Arrays
PARELEC '04 Proceedings of the international conference on Parallel Computing in Electrical Engineering
Optimized Data-Reuse in Processor Arrays
ASAP '04 Proceedings of the Application-Specific Systems, Architectures and Processors, 15th IEEE International Conference
Hierarchical algorithm partitioning at system level for an improved utilization of memory structures
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
EUC'07 Proceedings of the 2007 international conference on Embedded and ubiquitous computing
Maximum edge matching for reconfigurable computing
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
Physically-aware exploitation of component reuse in a partially reconfigurable architecture
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
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In this paper we present a method to optimize the overhead in dynamically reconfigurable computing systems. Applications are considered to be partitioned into algorithmic blocks. Our method allows a reduction of overhead when reconfiguration between those blocks is required. For each block a variety of specifications is constructed using high level algorithmic transformations based on a partitioning method for nested loop programs. The partitioning method allows an efficient verification with the given design constraints. The specifications differ in resource usage and execution time. The reconfiguration costs are reduced by finding the best matching specifications of the algorithmic blocks. The specifications with the lowest reconfiguration cost are selected for implementation using the matching information as input for the implementation tools. Finally we present an optimal solution for a reconfigurable 2D mean filter. Two configurations with different filter sizes and word widths were implemented according to the matching specifications. We reduced the required logic area compared to the non-reconfigurable implementation and reduced significantly the reconfiguration costs.