A course in number theory and cryptography
A course in number theory and cryptography
Systolic Array Implementation of Euclid's Algorithm for Inversion and Division in GF (2m)
IEEE Transactions on Computers
On Computing Multiplicative Inverses in GF(2/sup m/)
IEEE Transactions on Computers
Comparison of arithmetic architectures for Reed-Solomon decoders in reconfigurable hardware
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
Efficient Computation of Multiplicative Inverses for Cryptographic Applications
ARITH '01 Proceedings of the 15th IEEE Symposium on Computer Arithmetic
| Hi-index | 0.00 |
We propose two hardware inverters for calculating the multiplicative inverses in finite fields GF(2m): one produces a result in every O(m) time using O(m) area; and the other produces a result in every O(1) time using O(m2) area. While existing O(m)-time inverters require at least two shift registers in the datapath, the proposed O(m)-time implementation uses only one, thus costing less hardware. By exploiting the idea used in the O(m)-time inverter and developing a new way of controlling the dataflow, we also design a new O(1)-time inverter that works faster but costs less hardware than the best previously proposed O(1)-time implementation with the same area-time complexity.