Burst Error Detection Hybrid ARQ with Crosstalk-Delay Reduction for Reliable On-chip Interconnects

Authors:
Bo Fu;Paul Ampadu
Affiliations:
-;-
Venue:
DFT '09 Proceedings of the 2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
Year:
2009

Citing 0
Cited 2

Product code schemes for error correction in MLC NAND flash memories

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Design of a novel error correction coding with crosstalk avoidance for reliable on-chip interconnection link

International Journal of Computer Applications in Technology

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Abstract

We present a hybrid ARQ (HARQ) scheme using single-error correcting burst-error detecting (SEC-BED) codes to address multiple errors in nanoscale on-chip interconnects. For a given residual flit error rate requirement, the proposed HARQ method yields 20% energy improvement over other burst error correction schemes. By further integrated with skewed transitions, the proposed HARQ method can efficiently improve the error resilience against burst errors and also reduce delay uncertainty caused by capacitive coupling. The low overhead of our approach makes it suitable for implementation in reliable and energy efficient on-chip communication.