Area-efficient Reed-Solomon decoder design for optical communications
IEEE Transactions on Circuits and Systems II: Express Briefs
VLSI implementation of BCH error correction for multilevel cell NAND flash memory
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Efficient Generalized Minimum-distance Decoders of Reed-Solomon Codes
Journal of Signal Processing Systems
Nonlinear multi-error correction codes for reliable MLC NAND flash memories
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Hi-index | 0.01 |
In this paper, a new high-speed VLSI architecture for decoding Reed-Solomon codes with the Berlekamp-Masseyalgorithm is presented. The proposed scheme uses the fully folded systolic architecture in which a single array of processors, computes both the error-locator and the error-evaluator polynomials. The proposed scheme utilizes the folding property of systolic array architectures and reduces the number of multipliers and adders drastically at the expense of some compromise in the speed. More interestingly, the proposed architecture requires approximately 60% fewer multipliers and a simpler control structure than the popular RiBM architecture. The reduction in the number of multipliers and adders in the proposed architecture leads to smaller silicon area and lower power consumption.