CRT-based high-speed parallel architecture for long BCH encoding

Authors:
Hao Chen
Affiliations:
Software Engineering Institute, East China Normal University, Shanghai, China
Venue:
IEEE Transactions on Circuits and Systems II: Express Briefs
Year:
2009

Citing 4
Cited 0

Finite field for scientists and engineers

Finite field for scientists and engineers
A two-step computation of cyclic redundancy code CRC-32 for ATM networks

IBM Journal of Research and Development
Theory of Information and Coding

Theory of Information and Coding
High-speed architectures for parallel long BCH encoders

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Quantified Score

Hi-index	0.00

Visualization

Abstract

Bose-Chaudhuri-Hocquenghen (BCH) error-correcting codes are now widely used in communication system and digital technology. The direct linear feedback shifted register (LFSR)-based encoding of a long BCH code suffers from the large fan-out effect of some XOR gates. This makes the LFSR-based encoders of long BCH codes not keep up with the data transmission speed in some applications. The technique for eliminating the large fan-out effect by J-unfolding method and some algebraic manipulation has been proposed. In this brief, we present a Chinese remainder theorem (CRT)-based parallel architecture for long BCH encoding. Our novel technique can be used to eliminate the fan-out bottleneck. The only restriction on the speed of long BCH encoding of our CRT-based architecture is log2 N, where N is the length of the BCH code.