Fault tolerant bus architecture for deep submicron based processors
ACM SIGARCH Computer Architecture News - Special issue: Workshop on architectural support for security and anti-virus (WASSA)
The arithmetic cosine transform: exact and approximate algorithms
IEEE Transactions on Signal Processing
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In this paper, we put forth a novel frequencydomain BIST approach towards instruction executionlevel testing. This BIST scheme employs numbertheoretic transform to obtain the spectrum of thecontrol sequences (generated by the processor controlunit, the Finite State Machine) of the instructionsduring execution to detect stuck-at and transientfaults and weak logic signals. The scheme involvesfour level logic to detect weak-0 and weak-1 logicsignals. Weak signals lead to degradation of the noisemargin, particularly in DSM technology based multi-GHzprocessors. This novel concept is verified bysimulation using FSM benchmark circuits. The fourlevel logic has been successfully simulated in Spice,and the results have been presented. Near 100% faultcoverage has been achieved. The overall functioningof this test scheme to detect transient faults and signalintegrity faults is also shown.