Fault modeling and simulation for crosstalk in system-on-chip interconnects
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
LI-BIST: A Low-Cost Self-Test Scheme for SoC Logic Cores and Interconnects
VTS '02 Proceedings of the 20th IEEE VLSI Test Symposium
At-Speed On-Chip Diagnosis of Board-Level Interconnect Faults
ETS '04 Proceedings of the European Test Symposium, Ninth IEEE
Three-dimensional integrated circuits
IBM Journal of Research and Development - Advanced silicon technology
Interconnects in the third dimension: design challenges for 3D ICs
Proceedings of the 44th annual Design Automation Conference
Testing for Faults in Wiring Networks
IEEE Transactions on Computers
Developing mesochronous synchronizers to enable 3D NoCs
Proceedings of the conference on Design, automation and test in Europe
Is 3D chip technology the next growth engine for performance improvement?
IBM Journal of Research and Development
Test Challenges for 3D Integrated Circuits
IEEE Design & Test
Testing TSV-based three-dimensional stacked ICs
Proceedings of the Conference on Design, Automation and Test in Europe
Full-chip TSV-to-TSV coupling analysis and optimization in 3D IC
Proceedings of the 48th Design Automation Conference
Switching activity generation with automated BIST synthesis for performance testing of interconnects
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Three-dimensional (3D) integration is a key technology for systems whose performance and power requirements cannot be achieved by traditional silicon technologies. 3D chips consist of two or more stacked silicon dies connected by short inter-die wires called Thru-Silicon-Vias (TSVs). Despite its potential, the poor reliability and yield, thermal management and testing issues remain major challenges of 3D integration. We address the TSV interconnect test challenge of 3D chips by using Interconnect Built-In Self-Test (IBIST) techniques. The proposed test strategy must sensitize structural faults like opens and shorts, and delay faults due to crosstalk. A possible approach is the well-known Maximum Aggressor Fault (MAF) model. Unfortunately, this model is too conservative and it leads to long test sequences and non-negligible hardware costs. Therefore, we present an alternative solution: the Kth-Aggressor Fault (KAF) model. In our model, aggressors of victim wires are neighboring wires within an optimized distance order K. The aggressor order K is technology-dependent and is determined such that the test times are minimal and the fault coverage is maximal. KAF-based IBIST implementation targeting TSV tests occupies three times less area than similar MAF-/marching-based implementations. We also propose a reconfigurable KAF-based IBIST implementation where tests can be performed using different aggressor orders K. Although the reconfigurable IBIST area is significant, interconnect tests during system lifetime can be performed using lower aggressor orders, reducing test duration and improving TSV availability.