SOC test architecture optimization for signal integrity faults on core-external interconnects
Proceedings of the 44th annual Design Automation Conference
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Highly compact interconnect test patterns for crosstalk and static faults
IEEE Transactions on Circuits and Systems II: Express Briefs
Highly compact interconnect test patterns for crosstalk and static faults
IEEE Transactions on Circuits and Systems II: Express Briefs
A unified detection scheme for crosstalk effects in interconnection bus
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Self-calibrated energy-efficient and reliable channels for on-chip interconnection networks
Journal of Electrical and Computer Engineering - Special issue on Networks-on-Chip: Architectures, Design Methodologies, and Case Studies
Kth-Aggressor Fault (KAF)-based Thru-Silicon-Via Interconnect Built-In Self-Test and Diagnosis
Journal of Electronic Testing: Theory and Applications
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For deep sub-micron system-on-chips (SoC), interconnects are critical determinants of performance, reliability and power. Buses and long interconnects being susceptible to crosstalk noise, may lead to functional and timing failures. Existing at-speed interconnect crosstalk test methods are based on either (i) inserting dedicated interconnect self-test structures (leading to significant area overhead), or (ii) using existing logic BIST structures (e.g.,LFSRs), which often result in poor defect coverage. Additionally, it has been shown that the power consumed during testing can potentially become a significant concern.In this paper, we present Logic-Interconnect BIST (LI-BIST), a omprehensive self-test solution for both the logic of the cores and the SoC interconnects. LI-BIST reuses existing LFSR structures but generates high-quality tests for interconnect crosstalk defects, while minimizing area over-head and interconnect power consumption. On applying LI-BIST to a DSP chip, we achieved crosstalk defect coverage of 99.7% for the interconnects and single stuck-at-fault overage of 91.36% for the logic cores, while incurring an area overhead of only 4% over conventional logic BIST.