A Statistical Fault Coverage Metric for Realistic Path Delay Faults
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
SRAM delay fault modeling and test algorithm development
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Ramp Voltage Testing for Detecting Interconnect Open Faults
IEICE - Transactions on Information and Systems
Parallel X-fault simulation with critical path tracing technique
Proceedings of the Conference on Design, Automation and Test in Europe
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Delay faults are an increasingly important testchallenge. Traditional open and bridge fault models areincomplete because only the functional fault or a subset ofdelay fault are modeled. In this paper, we propose acircuit level model for resistive open and bridge faults. Allpossible fault behaviors are illustrated and a generalresistive bridge delay calculation method is proposed. Thenew models are practical and easy to use. Fault simulationresults show that the new models help the delay test tocatch more bridge faults.