A built-in redundancy-analysis scheme for RAMs with 2D redundancy using 1D local bitmap
Proceedings of the conference on Design, automation and test in Europe: Proceedings
A Built-In Redundancy-Analysis Scheme for Random Access Memories with Two-Level Redundancy
Journal of Electronic Testing: Theory and Applications
ProTaR: an infrastructure IP for repairing RAMs in system-on-chips
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
On topology reconfiguration for defect-tolerant NoC-based homogeneous manycore systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
DABISR: a defect-aware built-in self-repair scheme for single/multi-port RAMs in SoCs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special section on the ACM IEEE international conference on formal methods and models for codesign (MEMOCODE) 2009
ReBISR: a reconfigurable built-in self-repair scheme for random access memories in SOCs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A built-in repair analyzer with optimal repair rate for word-oriented memories
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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CRESTA is a built-in self-repair analyzer (BISRA)used for repair of bit-oriented memories, which canrepair all repairable bit-oriented memories with availablespare resource. This paper enhances CRESTA to supportembedded word-oriented memories. Within each readcycle of at-speed memory BIST, the analyzer is able tohandle multiple-bit failure in a word-oriented memory.Furthermore, to reduce area overhead, the proposedanalyzer is reconfigurable to process all repair strategiesin serial. To cover all repair strategies efficiently, wepropose a branch and bound algorithm to select repairstrategies.