Efficient spare allocation in reconfigurable arrays
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
A Built-In Self-Repair Analyzer (CRESTA) for embedded DRAMs
ITC '00 Proceedings of the 2000 IEEE International Test Conference
A BIRA Algorithm for Embedded Memories with 2-D Redundancy
MTDT '05 Proceedings of the 2005 IEEE International Workshop on Memory Technology, Design, and Testing
Post-Packaging Auto Repair Techniques for Fast Row Cycle Embedded DRAM
ITC '04 Proceedings of the International Test Conference on International Test Conference
A built-in redundancy-analysis scheme for RAMs with 2D redundancy using 1D local bitmap
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Efficient BISR Techniques for Word-Oriented Embedded Memories with Hierarchical Redundancy
ICIS-COMSAR '06 Proceedings of the 5th IEEE/ACIS International Conference on Computer and Information Science and 1st IEEE/ACIS International Workshop on Component-Based Software Engineering,Software Architecture and Reuse
A Built-In Redundancy-Analysis Scheme for Self-Repairable RAMs with Two-Level Redundancy
DFT '06 Proceedings of the 21st IEEE International Symposium on on Defect and Fault-Tolerance in VLSI Systems
An Integrated Built-In Test and Repair Approach for Memories with 2D Redundancy
ETS '07 Proceedings of the 12th IEEE European Test Symposium
Economic Aspects of Memory Built-in Self-Repair
IEEE Design & Test
A Sharable Built-in Self-repair for Semiconductor Memories with 2-D Redundancy Scheme
DFT '07 Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems
A Fault-Driven, Comprehensive Redundancy Algorithm
IEEE Design & Test
Efficient built-in redundancy analysis for embedded memories with 2-d redundancy
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
EOF: efficient built-in redundancy analysis methodology with optimal repair rate
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A built-in repair analyzer with optimal repair rate for word-oriented memories
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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With the growth of memory capacity and density, test cost and yield improvement are becoming more important. In the case of embedded memories for systems-on-a-chip (SOC), built-in redundancy analysis (BIRA) is widely used as a solution to solve quality and yield issues by replacing faulty cells with extra good cells. However, previous BIRA approaches focused mainly on embedded memories rather than commodity memories. Many BIRA approaches require extra hardware overhead to achieve the optimal repair rate, which means that 100% of solution detection is guaranteed for intrinsically repairable dies, or they suffer a loss of repair rate to minimize the hardware overhead. In order to achieve both low area overhead and optimal repair rate, a novel BIRA approach is proposed and it builds a line-based searching tree. The proposed BIRA minimizes the storage capacity requirements to store faulty address information by dropping all unnecessary faulty addresses for inherently repairable die. The proposed BIRA analyzes redundancies quickly and efficiently with optimal repair rate by using a selected fail count comparison algorithm. Experimental results show that the proposed BIRA achieves optimal repair rate, fast analysis speed, and nearly optimal repair solutions with a relatively small area overhead.