A Sharable Built-in Self-repair for Semiconductor Memories with 2-D Redundancy Scheme

Authors:
Swapnil Bahl
Affiliations:
STMicroelectronics Ltd, India
Venue:
DFT '07 Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems
Year:
2007

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Abstract

Newer technologies like 90 nm and 65 nm bring with them new challenges: longer time to process maturity, higher defect densities and poorer yields. The quality of test and repair determines the design's final yield and profitability. With increasing amount of memory on the chip, the need for an efficient and fast converging perfect algorithm for memory repair is increasing becoming important. In this paper, a perfect algorithm is presented for standalone repairable memories as well as for situations where redundancy is shared between different memories. The proposed BISR is composed of Built-in self-test (BIST) and built-in redundancy analysis (BIRA) module. The BISR module has a low overhead - about 5.05 % of memories area for a typical automotive chip. The proper redundancy scheme and the proposed BIRA algorithm ensure a high repair rate for the SOC and shorter test times as well as optimized area and maximum performance.