Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
A comparative study of power efficient SRAM designs
GLSVLSI '00 Proceedings of the 10th Great Lakes symposium on VLSI
Layout-driven memory synthesis for embedded systems-on-chip
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low Power SRAM Design using Hierarchical Divided Bit-Line Approach
ICCD '98 Proceedings of the International Conference on Computer Design
An Environment for Exploring Low Power Memory Configurations in System Level Design
ICCD '99 Proceedings of the 1999 IEEE International Conference on Computer Design
Improving the Efficiency of Memory Partitioning by Address Clustering
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
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Memory partitioning has proved to be a promising solution to reduce energy consumption in complex SoCs. Memory partitioning comes in different flavors, depending on the specific domain of usage and design constraints to be met. In this paper, we consider a technique that allows us to customize the architecture of physically partitioned SRAM macros according to the given application to be executed. We present design solutions for the various components of the partitioned memory architecture, and develop a memory generator for automatically generating layouts and schematics of the optimized memory macros. Experimental results, collected for two different case studies, demonstrate the efficiency of the architecture and the usability of the prototype memory generator. In fact, the achieved energy savings w.r.t. implementations featuring monolithic architectures, are around 43% for a memory macro of 1KByte, and around 45% for a memory macro of 8KByte.