Low-power digital systems based on adiabatic-switching principles
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
Energy recovery clocking scheme and flip-flops for ultra low-energy applications
Proceedings of the 2003 international symposium on Low power electronics and design
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Timing Optimization in Sequential Circuit by Exploiting Clock-Gating Logic
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Low-swing differential conditional capturing flip-flop for LC resonant clock distribution networks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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A significant fraction of the total power in highly synchronous systems is dissipated over clock networks. Hence, low-power clocking schemes are promising approaches for low-power design. We propose four novel energy recovery clocked flip-flops that enable energy recovery from the clock network, resulting in significant energy savings. The proposed flip-flops operate with a single-phase sinusoidal clock, which can be generated with high efficiency. In the TSMC 0.25-µm CMOS technology, we implemented 1024 proposed energy recovery clocked flip-flops through an H-tree clock network driven by a resonant clock-generator to generate a sinusoidal clock. Simulation results show a power reduction of 90% on the clock-tree and total power savings of up to 83% as compared to the same implementation using the conventional square-wave clocking scheme and flip-flops. Using a sinusoidal clock signal for energy recovery prevents application of existing clock gating solutions. In this paper, we also propose clock gating solutions for energy recovery clocking. Applying our clock gating to the energy recovery clocked flip-flops reduces their power by more than 1000× in the idle mode with negligible power and delay overhead in the active mode. Finally, a test chip containing two pipelined multipliers one designed with conventional square wave clocked flip-flops and the other one with the proposed energy recovery clocked flip-flops is fabricated and measured. Based on measurement results, the energy recovery clocking scheme and flip-flops showa power reduction of 71% on the clock-tree and 39% on flip-flops, resulting in an overall power savings of 25% for the multiplier chip.