Low-power digital systems based on adiabatic-switching principles
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
Low-power design techniques for high-performance CMOS adders
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the 40th annual Design Automation Conference
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Power consumption has become a critical design criterion for integrated circuits given the growing importance of portable battery-operated devices. A typical CMOS gate driven by power supply (VDD) draws energy equal to CLVDD2 during every cycle of operation. We propose a new approach to recycle the charge with an adiabatic charge pump that moves the slower adiabatic components away from the critical path of logic. The critical path of the system, and hence the delay, do not change. This is achieved by overlapping the adiabatic charge pump delays with the computing path logic delays. Many embedded high performance applications such as digital signal processing (DSP), which exhibit datapath parallelism, are ideal candidates for this scheme. The proposed method has been implemented in DSP computations. SPICE simulations-based results indicate that the proposed scheme reduces energy consumption in these DSP circuits by as much as 18% (on average 9.94%) with no perceptible loss in performance. The area penalty for these energy savings are in the 1%-2% range, The leakage energy reduction in 45-nm BPTM averages 46 %.