Energy recovery strategy for low power CMOS circuits design

Authors:
Anand Paul;A. Ebenezer Jeyakumar;P. N. Neelakantan;K. John Pratheep
Affiliations:
Government College of Technology, Coimbatore, TN, India;Government College of Technology, Coimbatore, TN, India;Government College of Technology, Coimbatore, TN, India;Government College of Technology, Coimbatore, TN, India
Venue:
ICECS'03 Proceedings of the 2nd WSEAS International Conference on Electronics, Control and Signal Processing
Year:
2003

Citing 6
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Abstract

In view of changing the type of energy conversion in CMOS circuits, this paper investigates low power CMOS circuit design which adopts gradually changing power clock. First, we discuss the algebraic expressions and the corresponding properties of clocked power signals, then a clocked CMOS gate structure is presented. The PSPICE simulations demonstrate the low power characteristic of clocked CMOS circuits using trapezoidal power-clock. Finally, this paper also explores the design of sequential circuit, which adopts flip-flop with clocked power.