Power Optimization of Delay Constrained CMOS Bus Drivers

Authors:
S. Caufape;J. Figueras
Affiliations:
Departament d'Enginyeria Electrònica, Universitat Politècnica de Catalunya, Diagonal 647, Planta9, 08028 Barcelona;Departament d'Enginyeria Electrònica, Universitat Politècnica de Catalunya, Diagonal 647, Planta9, 08028 Barcelona
Venue:
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Year:
1996

Citing 2
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Abstract

The design automation of minimum power delay-constrained CMOS Bus Drivers for library-based (standard cells) and full-custom design environments is presented in this paper. The effect of the short circuit current consumption is taken into account in the total power evaluation. The proposed methodology is applied to efficiently find the optimum selection of buffers for any given bus load and delay constraint. Analytical predictions and results show good agreements with time costly SPICE simulations and reflect the need of variable taper factors for low power buffers in synchronous CMOS digital circuits.