The design and analysis of VLSI circuits
The design and analysis of VLSI circuits
Practical implementation of charge recovering asymptotically zero power CMOS
Proceedings of the 1993 symposium on Research on integrated systems
Low-power digital systems based on adiabatic-switching principles
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
Introduction to VLSI Systems
Asymptotically zero energy computing using split-level charge recovery logic
Asymptotically zero energy computing using split-level charge recovery logic
Energy recovery for the design of high-speed, low-power static RAMs
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
Comparison of high speed voltage-scaled conventional and adiabatic circuits
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
Clock-Powered CMOS: A Hybrid Adiabatic Logic Style for Energy-Efficient Computing
ARVLSI '99 Proceedings of the 20th Anniversary Conference on Advanced Research in VLSI
Quality of EDA CAD Tools: Definitions, Metrics and Directions
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
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Energy recovery, as a means to trade off power dissipation for performance in CMOS logic circuits, is analyzed and investigated. A mathematical model is presented to estimate the efficiency for two energy-recovery approaches under varying conditions of voltage swing, transition time, and MOS device parameters. This model can be directly compared to the well-known model for supply-voltage scaling, which is the prevalent method for trading power dissipation for performance. The two models are evaluated against SPICE simulations. Excluding body effects, which would not be present in CMOS process technologies such as Silicon-On-Insulator (SOI), the simulations and the equations agree to within 10%. The simulations also indicate that energy recovery, when implemented with circuit techniques such as bootstrapping, can significantly outperform the supply-voltage-scaled approach across a wide range of operating frequencies. To further investigate this result, two eight-bit adder designs, one based on supply-voltage scaling and the other on energy recovery, are simulated and compared.