Logic testing and design for testability
Logic testing and design for testability
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
The complexity of theorem-proving procedures
STOC '71 Proceedings of the third annual ACM symposium on Theory of computing
Generalized Hopfield Neural Network for Concurrent Testing
IEEE Transactions on Computers
Polynomial Time Testability of Circuits Generated by Input Decomposition
IEEE Transactions on Computers
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The computational complexity of fault detection problems and various controllability and observability problems for combinational logic circuits are analyzed. It is shown that the fault detection problem is still NP-complete for monotone circuits limited in fanout, i.e. when the number of signal lines which can out from a signal line is limited to two. It is also shown that the observability problem for unate circuits is NP-complete, but that the controllability problem for unate circuits can be solved in time complexity O(m), where m is the number of lines in a circuit. Two classes of circuits, called k-binate-bounded circuits and k-bounded circuits, are then introduced. For k-binate-bounded circuits the controllability problem is solvable in polynomial time, and for k-bounded circuits the fault detection problem is solvable in polynomial time, when kor=log p(m) for some polynomial p(m). The class of k-bounded circuits includes many practical circuits such as decoders, adders, one-dimensional cellular arrays, and two-dimensional cellular arrays.